Replacement of failed elements or lines in a memory array formed on a chip or substrate by the use of redundant elements or lines provided on the chip or substrate has been known. Redundancy techniques have generally used laser beams to blow fuses formed on a substrate at wafer levels. In this manner redundant elements are used to replace failing elements. Thereafter the wafer is diced into chips and the chips are mounted in a module. After completion of the module burn-in takes place. Any elements that fail burn-in are discarded or undergo disassembly of the module and expensive repairs.
A chip that integrates various kinds of circuits including logic circuits having memory arrays embedded therein poses special problems for circuit designers/testers who desire adequate testability of the embedded arrays since such chips have fewer input/output pins available to the circuit testers than is available in a chip having a stand alone memory.
To lower the cost of making memories by reducing testing expenses and improving memory yields, systems have been disclosed which are self testing and self repairing. One such system, sometimes known as an array built in self test (ABIST) system, is taught in U.S. Pat. No. 4,939,694, issued on Jul. 30, 1990, which uses substitute address tables and error correction code (ECC) techniques for correcting errors found in the memory cell. Another ABIST system, disclosed in European Patent No. 0 242 854, published on Oct. 28, 1987, replaces defective memory cells of a semiconductor memory with spare memory cells using an associative memory. U.S. Pat. No. 3,755,791, issued on Aug. 28, 1973, filed by L. M. Arzubi, and IBM Technical Disclosure Bulletin, Vol. 23, No. 8, pp. 3601 and 3602, entitled "Semiconductor Memory Redundancy at Module Level" by B. F. Fitzgerald and D. R. Whittaker, disclose the use of non-volatile cells for storing failing addresses semi-permanently. A further ABIST system is disclosed in U.S. patent application entitled "Built-In Self Test for Integrated Circuits" and having Ser. No. 07/576646, filed on Aug. 30, 1990, by E. L. Hedberg et al., wherein one dimensional failed address registers are used to store word addresses of defective cells of a memory array, i.e., redundant lines are provided which extend in only one direction parallel to the word lines of the array. U.S. patent application entitled "Method and Apparatus for Real Time Two Dimensional Redundancy Allocation" filed on Oct. 16, 1991, by E. L. Hedberg and G. S. Koch, having Ser. No. 07/777,877, discloses an ABIST system wherein two dimensional redundant lines are directly allocated in real time during final manufacturing testing to increase semiconductor chip yields U.S. patent application entitled "Low Voltage Programmable Storage Element", filed on Apr. 30, 1991, having Ser. No. 07/693,463, discloses programmable redundancy wherein resistance decreases in a programmable antifuse circuit are sensed.